The present invention relates to a video signal processing technique, and more particularly, it relates to a technique for displaying a video signal on a display device.
Recently, video signals have been dealt with as digital signals. Also, signals to be input to video equipment have been diversified and there are a variety of signals such as video system signals, PC system signals and signals for game equipment. With respect to each of these various signals, there are a large number of formats. Therefore, display devices for displaying video signals, such as a CRT (cathode-ray tube), a liquid crystal display and a PDP (plasma display panel), are required to be applicable to a larger number of formats of the video signals.
Also, a display device is required to have a function to display one of the various formats of the video signals but to simultaneously display a multi-screen through synthesis of a plurality of video signals. Furthermore, it is indispensable to perform resize processing for matching the numbers of pixels arranged in the vertical and horizontal directions in one screen of the video signal with the numbers of pixels of a display device or of a desired screen size.
In order to realize these functions, video signal processing circuits respectively corresponding to the formats of video signals to be input are conventionally designed, so as to construct a video signal processing system by combining these processing circuits. Accordingly, as the number of formats of processable video signals is increased, the circuit scale tends to increase. Furthermore, a large memory capacity is necessary for coping with a video signal format with a large screen size.